Integrated circuit fabrication processes typically have steps which transfer a pattern from a mask to a substrate by exposing selected portions of a resist covered substrate to radiation. The resist is sensitive to radiation which alters at least one characteristic of the resist. Although direct write schemes are used in some applications, the selective exposure is most frequently obtained by use of the mask. After exposure, selected portions of the resist, defined by the exposure, are removed and the now exposed underlying substrate material is subject to a process step, such as material removal by etching or ion implantation. The pattern should be accurately transferred from the mask to the substrate; that is, there should be minimal differences between the desired feature dimensions and the actual feature dimensions. Bi- and tri-level resists have been developed to facilitate accurate pattern transfer. See, for example, U.S. Pat. Nos. 4,521,274 and 4,244,799 issued to Reichmanis et al. and Fraser et al., respectively.
One dimension of special interest as device dimensions decrease is the gate width of a field effect transistor. This dimension is of great interest for device fabrication because it determines the electrical channel length of the transistor. The channel length is an important parameter in determining the electrical characteristics of the field effect transistors. At half micron or smaller dimensions, variations of the channel length from the desired value become a significant percentage of the channel length and are likely to produce significant deviations from the desired electrical characteristics of the transistor.
The channel length is determined primarily by the width of the gate structure which is obtained by patterning a layer of polysilicon or a tungsten silicide/polysilicon sandwich. Variations in the width of the polysilicon come from several factors of which the two most important are probably the lithography and etch processes. One factor contributing to linewidth variations in the etching process is believed to be a loading effect; that is, the etch rate depends upon the density of the features being etched or the exposed area. A consequence of this effect is that features on wafers with different percentages of exposed areas can have different average linewidths. (It is assumed that the different integrated circuits are being fabricated on the different wafers.) Additionally, on the same wafer, relatively isolated features may have linewidths that differ from those of more compactly situated features.
The presence of the photoresist used as an etch mask is an important parameter in determining the extent of the loading effect. It has been proposed that a dielectric, in the absence of photoresist, be used as the etch mask to reduce the magnitude of the loading effect. In this process, the dielectric is deposited after the polysilicon has been deposited for the gate but prior to the photoresist deposition. In particular, the photoresist is deposited and patterned. The pattern is transferred to the dielectric and the photoresist is stripped. The pattern is then transferred into the polysilicon using the dielectric as a hard mask. Contemplated dielectric materials include silicon oxide or nitride. However, nitride may not have the required etch selectivity with respect to polysilicon to act as a good etch mask. For those applications which form a salicide on the gate, it is necessary to remove the dielectric hard mask from the gate. More generally, it is desirable to remove the hard mask in order to minimize the gate stack height because the taller stacks make planarization more difficult for subsequent levels. However, it is difficult to strip oxide without significant loss of thermal oxide. Most dielectric materials are deposited conformally and do not significantly change the topography of the underlying layer. The resist thus has a thickness which is a function of the local topography. See, for example, L. K. White, Journal of the Electrochemical Society, July 1988, pp. 1844-1846, and S. Kaplan, Proceedings of the Microlithography Seminar, INTERFACE '90, pp. 307-314. Unfortunately, the variations in resist thickness can be large enough to cause significant variations in linewidths. Variations in thickness can produce standing wave effects. There may also be reflective notching which is produced by resist variations together with the effects of curvature of the underlying substrate.